In various systems and applications, secure Integrated Circuits (ICs) store sensitive information, e.g., in Flash memory or other Non-Volatile Memory (NVM). Various techniques are known in the art for preventing unauthorized access to information stored on NVM. For example, U.S. Pat. No. 8,151,072, whose disclosure is incorporated herein by reference, describes an electronic device including a NVM having a plurality of words 1 . . . N whose read and/or write access can be locked. A protection register is formed of two protection words A and B, which are alternately active and inactive during successive locking of words 1 . . . N of the programmable memory. The state of the protection register is defined by the active word. An initially active word is not deleted until the content thereof has been copied into the inactive word. Once the content has been altered in accordance with the lock command, the initially inactive word becomes the active word of the protection register.
U.S. Pat. No. 9,202,073, whose disclosure is incorporated herein by reference, describes security measures for shielding or protecting data or sensitive signals on an Integrated Circuit (IC). The disclosed systems and methods can allow erasing sensitive data when access is not locked, locking out access to sensitive data during normal operations through both indirect and direct means, and shielding sensitive signals from invasive probing or manipulation.
U.S. Pat. No. 9,262,259, whose disclosure is incorporated herein by reference, describes techniques for One-Time Programmable (OTP) integrated circuit security. An example method includes sampling values of multiple OTP memory arrays and comparing the sampled value of each OTP memory array with the sampled value of each other OTP memory array and with an un-programmed OTP memory array value. The method further includes determining if an integrated circuit performance fault has occurred based on the compared sampled values.
U.S. Pat. No. 5,954,818, whose disclosure is incorporated herein by reference, describes a method of writing to memory cells in a Flash memory device that includes first and second memory arrays. The first memory array includes memory blocks. The second independent memory array includes block lock-bits each corresponding to one of the memory blocks. The method of writing to a memory cell in one of the memory blocks of the first memory array includes issuing a command to write to the memory cell, determining if a corresponding block lock-bit in the second independent memory array is set, and writing to the memory cell if the corresponding block lock-bit is not set.
U.S. Pat. No. 6,073,243, whose disclosure is incorporated herein by reference, describes a Flash memory device including a first memory array, block locking circuitry, and control circuitry. The memory array includes a plurality of memory blocks. The block locking circuitry includes a plurality of block lock-bits and a master lock-bit. Each block lock-bit corresponds to one of the plurality of memory blocks and indicates whether the corresponding memory block is locked. The master lock-bit indicates whether the plurality of block lock-bits are locked. Control circuitry is configured to receive a passcode that causes the control circuitry to override the master lock-bit.